1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to methods of fabricating a integrated circuit devices including gate insulating layers and related devices.
2. Description of the Related Art
High integration of semiconductor memory devices such as DRAM devices has resulted in a reduction in the size of transistors. As the length of a gate decreases, the thickness of a gate insulating layer (such as a gate oxide layer) may be reduced to increase the operational speed of a semiconductor device. However, a decrease in the thickness of the gate insulating layer may also increase a frequency of breakdowns because decreasing the thickness of the gate insulating layer generally results in a lower breakdown voltage. In addition, different areas of a memory device may have varying performance requirements. Therefore, a desired thickness of a gate insulating layer may vary from point to point on a semiconductor device based on desired performance characteristics.
For example, if gate insulating layers in a cell array region and a peripheral circuit region have different thicknesses, it may be possible to improve operational features and reliability of the device. Typically, performance and reliability can be improved if the cell array region has a gate insulating layer with a greater thickness than the peripheral circuit region. More specifically, because of advances in highly integrated semiconductor devices such as DRAM devices, the area of the cell array region of such devices has increased in size compared to the peripheral circuit region. If all of the gate insulating layers formed on a chip have the same thickness, a breakdown may occur first in a gate insulating layer positioned on the cell array region and the semiconductor device may lose reliability or fail to operate at all. This problem may be reduced by increasing thicknesses of the gate insulating layers formed on the cell array region in comparison to gate insulating layers formed on the peripheral circuit region.
FIGS. 1A through 1D are cross-sectional views illustrating a semiconductor device having gate oxide layers of different thicknesses fabricated according to a conventional method. In the structure shown in FIGS. 1A through 1D, the gate oxide layer formed on a left region TK is thicker compared to the gate oxide layer formed on a right region TI. As shown in FIG. 1A, a semiconductor substrate 10, e.g. a silicon substrate, having a trench 11 is first oxidized to obtain a first gate oxide layer 13. The first gate oxide layer 13 may be about 10 nm thick. Next, as shown in FIG. 1B, a photoresist pattern 15 is formed on a portion of the first gate oxide layer 13 in the TK region. A portion of the first gate oxide layer 13 is then etched from the TI region. As a result, the thickness of the first gate oxide layer 13 remaining on the TI region is thinner compared to that on the TK region.
The photoresist pattern 15 is removed from the TK region as shown in FIG. 1C. The first gate oxide layer 13 is etched such that the first gate oxide layer 13 is removed from the TI region. Because the photoresist pattern has been removed, the portion of the first gate oxide layer 13 on the TK region is also etched and the thickness of the gate oxide layer 13 in the TK region is reduced. Next, referring to FIG. 1D, the semiconductor substrate 10 is oxidized again to form a second gate oxide layer 17 on the TI. During this oxidation step, the thickness of the first gate oxide layer 13 on the TK region is increased. Through the above method, the first gate oxide layer 13 on the TK region can have a thickness greater than that of the second gate oxide layer 17 on the TI region. The resulting semiconductor device can thus have gate oxide layers with different thicknesses.
The first gate oxide layer 13 remaining on the TK region may, however, be contaminated when the first gate oxide layer 13 is selectively removed from the TI region (see FIGS. 1B and 1C). This contamination may degrade the operational characteristics of the semiconductor device.